Publications

Found 2 results
Filters: Keyword is circuit timing information  [Clear All Filters]
2005
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
2004
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Diagnosis of hold time defects”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.