Publications

Found 231 results
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D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Temporofunctional crosstalk noise analysis, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
C. - W. Chang, Wang, K., and Marek-Sadowska, M., Layout-driven hot-carrier degradation minimization using logic restructuring techniques, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
S. - C. Chang and Marek-Sadowska, M., Perturb And Simplify: Multi-level Boolean Network Optimizer, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
C. - W. Chang, Hu, B., and Marek-Sadowska, M., In-place delay constrained power optimization using functional symmetries, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Fast Boolean optimization by rewiring, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., A new reasoning scheme for efficient redundancy addition and removal, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., An efficient algorithm for local don't care sets calculation, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667.
S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., Perturb and simplify: multilevel Boolean network optimizer, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
D. Chang and Marek-Sadowska, M., Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Circuit optimization by rewiring, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
D. Chang, Lee, T. - C., Marek-Sadowska, M., Aikyo, T., and Cheng, K. - T., A Test Synthesis Approach To Reducing Ballast Dft Overhead, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
C. - W. Chang, Cheng, C. - K., Suaris, P., and Marek-Sadowska, M., Fast post-placement rewiring using easily detectable functional symmetries, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Layout Driven Logic Synthesis for FPGAs, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
D. Chang and Marek-Sadowska, M., Partitioning sequential circuits on dynamically reconfigurable FPGAs, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
S. - C. Chang, Cheng, D. I., and Marek-Sadowska, M., Minimizing ROBDD size of incompletely specified multiple output functions, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
C. - W. Chang and Marek-Sadowska, M., Theory of wire addition and removal in combinational Boolean networks, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
C. - W. Chang and Marek-Sadowska, M., Who are the alternative wires in your neighborhood? (alternative wires identification without search), in GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI, 2001, pp. 103–108.
S. - C. Chang and Marek-Sadowska, M., Technology mapping and circuit depth optimization for field programmable gate arrays, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Postlayout logic restructuring using alternative wires, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
S. - C. Chang and Marek-Sadowska, M., Perturb and simplify: optimizing circuits with external don't cares, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
C. - W. Chang and Marek-Sadowska, M., ATPG-based logic synthesis: an overview, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
D. Chang, Lee, T. - C., Cheng, K. - T., and Marek-Sadowska, M., Functional scan chain testing, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
C. - W. Chang and Marek-Sadowska, M., Single-pass redundancy-addition-and-removal, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
S. - C. Chang and Marek-Sadowska, M., Technology mapping via transformations of function graphs, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.

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