| Title | Layout Generator for Transistor-Level High-Density Regular Circuits |
| Publication Type | Journal Article |
| Year of Publication | 2010 |
| Authors | Yi-Wei Lin, Marek-Sadowska, M, Maly, W |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 29 |
| Pagination | 197 -210 |
| Date Published | feb. |
| ISSN | 0278-0070 |
| Keywords | automatic place, circuit layout, double-gate transistor-array-based layout, integrated circuit interconnections, integrated circuit layout, interconnects, layout generator, metal layers, network routing, optical proximity correction free process, route strategy, routing flexibility, transistor footprint, transistor-level high-density regular circuits |
| Abstract | In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate, transistor-array-based layout. Interconnects on all metal layers are strictly parallel and can be manufactured by an optical proximity correction free process. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced. |
| DOI | 10.1109/TCAD.2009.2035580 |
