Found 4 results
Search results for nandakumar  [Reset Search]
V. S. Nandakumar and M. Marek-Sadowska, “A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures”, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, p. 266 -277, 2012.
V. S. Nandakumar and M. Marek-Sadowska, “Layout effects in fine grain 3D integrated regular microprocessor blocks”, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, p. 639 -644.
V. S. Nandakumar and M. Marek-Sadowska, “Low power, high throughput network-on-chip fabric for 3D multicore processors”, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, p. 453 -454.
V. S. Nandakumar, D. Newmark, Y. Zhan, and M. Marek-Sadowska, “Statistical static timing analysis flow for transistor level macros in a microprocessor”, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, p. 163 -170.