Logic synthesis for engineering change

TitleLogic synthesis for engineering change
Publication TypeJournal Article
Year of Publication1999
AuthorsLin, C-C, Chen, K-C, Marek-Sadowska, M
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pagination282 -292
Date Publishedmar
Keywordsautomatic test pattern generation, binary decision diagrams, Boolean functions, CAD, circuit CAD, design specifications, digital integrated circuits, engineering changes, integrated circuit design, logic CAD, logic minimization techniques, logic synthesis algorithms, minimisation of switching nets, multiple-error diagnosis, very large scale integration, VLSI, VLSI design
AbstractDuring the process of very large scale integration design, specifications are often changed. To preserve as large a portion of the engineering effort as possible, it is desirable that such changes will not lead to a very different design. In this work, we consider logic synthesis algorithms for handling engineering changes. To solve it, we propose a combination of multiple-error diagnosis and logic minimization techniques. Given a new specification and an existing synthesized network, our algorithms first identify the candidate signals in the network, and then synthesize the candidate functions. The synthesis step utilizes the existing network as much as possible so that the new specification can be realized with minimal changes