STAR-ATPG: a high speed test pattern generator for large scan designs

TitleSTAR-ATPG: a high speed test pattern generator for large scan designs
Publication TypeConference Paper
Year of Publication1999
AuthorsTsai, K-H, Tompson, R, Rajski, J, Marek-Sadowska, M
Conference NameTest Conference, 1999. Proceedings. International
Keywordsautomatic test pattern generation, combinational circuits, deterministic patterns, efficient algorithm, fault clustering, fault simulation, high speed test pattern generator, large scan designs, logic testing, redundant faults, simpler fault simulation, STAR-ATPG, stuck-at faults, super gate extraction, synchronous circuits
AbstractStar test is a novel test pattern generation technique in which a few test vectors serve as centers of clusters for other test vectors which are derived by complementing at random their coordinates. By properly selecting the deterministic patterns as centers, the star tests have very high probability to detect most of the faults in a circuit. This paper presents an efficient algorithm to combine the star test approach with a traditional test pattern generator yielding a significant speed up of the ATPG process. With the new STAR-ATPG methodology, the major effort of the test generation is transferred from an computationally more complex test pattern generation process into simpler fault simulation. Experimental results on several large industrial designs demonstrate that a factor of 1.5-2.5 average speed up is achieved by the new method with the same abort limit. Also, STAR-ATPG achieves higher fault coverage than traditional ATPG under the same abort limit. To achieve the same fault coverage as STAR-ATPG, it requires the traditional method to increase the abort limit significantly and result in 5 times slower