| Title | Routing for array-type FPGA's |
| Publication Type | Journal Article |
| Year of Publication | 1997 |
| Authors | Wu, Y-L, Marek-Sadowska, M |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 16 |
| Pagination | 506 -518 |
| Date Published | may |
| ISSN | 0278-0070 |
| Keywords | algorithm, array-type FPGA, decaying effect, deterministic routing, field programmable gate arrays, greedy coupling heuristics, logic design, network routing, optimization cost function, routing, two-dimensional field programmable gate array, Xilinx architecture |
| Abstract | In this paper, the routing problem for two-dimensional (2-D) field programmable gate arrays of a Xilinx-like architecture is studied. We first propose an efficient one-step router that makes use of the main characteristics of the architecture. Then we propose an improved approach of coupling two greedy heuristics designed to avoid an undesired decaying effect, a dramatically degenerated router performance on the near completion stages. This phenomenon is commonly observed on results produced by the conventional deterministic routing strategies using a single optimization cost function. Consequently, our results are significantly improved on both the number of routing tracks and routing segments by just applying low-complexity algorithms. On the tested MCNC and industrial benchmarks, the total number of tracks used by the best known two-step global/detailed router is 28% more than that used by our proposed method |
| DOI | 10.1109/43.631213 |
