Logic rectification and synthesis for engineering change

TitleLogic rectification and synthesis for engineering change
Publication TypeConference Paper
Year of Publication1995
AuthorsLin, C-C, Chen, K-C, Cheng, DI, Marek-Sadowska, M
Conference NameDesign Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific
Date Publishedaug-1 sep
Keywordsautomatic synthesis, engineering change, logic CAD, logic design, logic minimization, minimisation of switching nets, multiple candidate signals, multiple-error diagnosis, specification change, VLSI design
AbstractIn the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design, so that a large part of engineering effort can be preserved. We treat this problem as a combination of multiple-error diagnosis and logic minimization problems. Given a new specification and an existing synthesized logic network, our algorithms modify the existing network minimally such that the new specification can be realized. In this paper, a new algorithm is developed to identify multiple candidate signals simultaneously from the existing network, such that appropriate modifications of these signals can rectify the specification change