- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Wire length prediction in constraint driven placement
Title | Wire length prediction in constraint driven placement |
Publication Type | Conference Paper |
Year of Publication | 2003 |
Authors | Liu, Q, Hu, B, Marek-Sadowska, M |
Conference Name | SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction |
Publisher | ACM |
Conference Location | New York, NY, USA |
ISBN Number | 1-58113-627-7 |
DOI | 10.1145/639929.639950 |