Power-Gating Aware Floorplanning

TitlePower-Gating Aware Floorplanning
Publication TypeConference Paper
Year of Publication2007
AuthorsJiang, H, Marek-Sadowska, M
Conference NameQuality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Date Publishedmarch
Keywordsintegrated circuit layout, leakage currents, leakage power, power-gated chips, power-gating aware floorplanning, thin-oxide decap
AbstractPower-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects, which are not considered in the earlier design stages. Ignoring those effects may result in suboptimal designs and potentially even nullify the intended power savings. In this paper, the authors propose a novel measure to efficiently capture the power-gating effects. The authors apply this measure in a floorplanner for power-gated chips. Experimental results show that the power-gating aware floorplanner can achieve 50% decap saving compared to a floorplanner unaware of power gating. Leakage power can be saved by inserting less decap, especially when thin-oxide decap are used due to the area constraint. The approach can reduce leakage power consumed by decap from 36mW to 9mW when area overhead is limited to about 19% of the total chip area