| Title | On-chip power-supply network optimization using multigrid-based technique |
| Publication Type | Journal Article |
| Year of Publication | 2005 |
| Authors | Wang, K, Marek-Sadowska, M |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 24 |
| Pagination | 407 - 417 |
| Date Published | march |
| ISSN | 0278-0070 |
| Keywords | back-mapping, circuit optimisation, decoupling capacitance, integrated circuit design, large-scale network, multigrid-based technique, network optimization, network routing, on-chip power-supply network optimization, power grid optimisation, power supply circuits, resistance-inductance-capacitance power-supply network, routing congestion, signal routing, time-varying networks, time-varying switching-current model |
| Abstract | In this paper, we present a novel multigrid-based technique for the problem of on-chip power-supply network optimization. The multigrid-based technique is applied to reduce a large-scale network to a much coarser one. The reduced network can be efficiently optimized. The solution for the original network is then quickly computed using a back-mapping process. Due to the adoption of an accurate resistance-inductance-capacitance power-supply network and time-varying switching-current model, our technique is capable of optimizing power grid and decoupling capacitance simultaneously. Experimental results show that large-scale power-supply networks with millions of nodes can be solved in a few minutes. The proposed technique not only speeds up significantly the optimization process, without compromising the quality of solutions, but also brings up a possibility of incorporating the power-supply network optimization into other physical design stages such as signal routing. |
| DOI | 10.1109/TCAD.2004.842802 |
