Gain-based technology mapping for discrete-size cell libraries

TitleGain-based technology mapping for discrete-size cell libraries
Publication TypeConference Paper
Year of Publication2003
AuthorsHu, B, Watanabe, Y, Marek-Sadowska, M
Conference NameDesign Automation Conference, 2003. Proceedings
Date Publishedjune
Keywordsarea-optimization heuristic, cell class, cellular arrays, constant-delay model, delays, discrete-size cell library, gain control, Gain-based technology mapping, integrated circuit design, logic design, logic effort, trade-off curve
AbstractIn this paper we describe a technology mapping technique based on the logical effort theory by I. Sutherland and R. Sproull (1991). First, we appropriately characterize a given standard cell library and extract from it a set of cell classes. Each cell-class is assigned a constant-delay model and corresponding load-bounds, which define the conditions of the delay model's validity. Next, we perform technology mapping using the classes determined in the first step. We propose several effective area-optimization heuristics which allow us to apply our algorithm directly to general graphs. Experimental results show that our gain-based mapping algorithm achieves reduced delay with less area, compared to the mapper in SIS by E. Sentovich et al. (1992). By adjusting the constant delay model associated with each class, we determine the area-delay trade-off curve. We achieve the best area-delay trade-off using a design-specific constant delay models.