| Title | On-chip power supply network optimization using multigrid-based technique |
| Publication Type | Conference Paper |
| Year of Publication | 2003 |
| Authors | Wang, K, Marek-Sadowska, M |
| Conference Name | Design Automation Conference, 2003. Proceedings |
| Date Published | june |
| Keywords | back-mapping process, integrated circuit design, integrated circuit noise, integrated circuit reliability, multigrid-based technique, on-chip power supply, on-chip switching, optimization, power supply circuits, power supply network, RLC circuits, RLC network, switching circuits, switching networks, system-on-chip, time-varying current sources |
| Abstract | In this paper, we present a multigrid-based technique for on-chip power supply network optimization. We reduce a large-scale network to a much coarser one which can be efficiently optimized. The solution for the original network is then quickly computed using a back-mapping process. We model the power grid by an RLC network and use time-varying current sources to capture the on-chip switching. Our technique is capable of optimizing power grid and decoupling capacitance simultaneously. Experimental results show that the proposed technique provides more robust and are-efficient solutions than those obtained by the earlier approaches. It also provides a significant speed-up and brings up a possibility of incorporating power supply network optimization into other physical design stages such as signal routing. |
| DOI | 10.1109/DAC.2003.1218843 |
