Publications

Found 8 results
Filters: Author is Chien-Chung Tsai  [Clear All Filters]
1993
C. - C. Tsai and Marek-Sadowska, M., Efficient minimization algorithms for fixed polarity AND/XOR canonical networks, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
1994
C. - C. Tsai and Marek-Sadowska, M., Boolean Matching Using Generalized Reed-Muller Forms, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
C. - C. Tsai and Marek-Sadowska, M., Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
C. - C. Tsai and Marek-Sadowska, M., Minimisation of fixed-polarity AND/XOR canonical networks, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.
1996
C. - C. Tsai and Marek-Sadowska, M., Generalized Reed-Muller forms as a tool to detect symmetries, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
C. - C. Tsai and Marek-Sadowska, M., Logic synthesis for testability, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.
C. - C. Tsai and Marek-Sadowska, M., Multilevel logic synthesis for arithmetic functions, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
1997
C. - C. Tsai and Marek-Sadowska, M., Boolean functions classification via fixed polarity Reed-Muller forms, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.