Publications

Found 1 results
Filters: Keyword is power minimization  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
V
A. Vittal and Marek-Sadowska, M., Low-power buffered clock tree design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.