Found 2 results
Filters: Keyword is integrated circuit noise and Author is Chao-Yang Yeh  [Clear All Filters]
C. - Y. Yeh and Merek-Sadowska, M., Timing-Aware Power-Noise Reduction in Placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 527 -541, 2007.
C. - Y. Yeh and Marek-Sadowska, M., Timing-aware power noise reduction in layout, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 627 - 634.