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A. Mukherjee and Marek-Sadowska, M., “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
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A. Todri and Marek-Sadowska, M., “Reliability Analysis and Optimization of Power-Gated ICs”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.