Publications

Found 5 results
Filters: Keyword is automatic test pattern generation and Author is Janusz Rajski  [Clear All Filters]
2009
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
2008
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Improving the Resolution of Single-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
2000
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
1999
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.