Publications
“Low-power buffered clock tree design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.
, “Crosstalk minimization for multiple clock tree routing”, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
, “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
, “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
, “A study of reliability issues in clock distribution networks”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
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