Publications

Found 2 results
Filters: Keyword is reliability  [Clear All Filters]
1997
A. Vittal and Marek-Sadowska, M., “Low-power buffered clock tree design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.
2008
A. Todri and Marek-Sadowska, M., “A study of reliability issues in clock distribution networks”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.