Publications

Found 2 results
Filters: Keyword is circuit layout CAD and Author is Singh, Amit  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
S
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., “Interconnect resource-aware placement for hierarchical FPGAs”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.