Publications

Found 2 results
Filters: Keyword is circuit layout CAD and Author is Chang, D.  [Clear All Filters]
Journal Article
D. Chang and Marek-Sadowska, M., Partitioning sequential circuits on dynamically reconfigurable FPGAs, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
Conference Paper
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., Time-multiplexed routing resources for FPGA design, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.