Publications
Found 37 results
Filters: Keyword is logic CAD and Author is Malgorzata Marek-Sadowska [Clear All Filters]
, “Timing driven placement”, in Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on, 1989, pp. 94 -97.
, “Delay and area optimization in standard-cell design”, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.
, “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.
, “Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
, “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
, “Graph based analysis of FPGA routing”, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
, “On computational complexity of a detailed routing problem in two dimensional FPGAs”, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
, “An efficient router for 2-D field programmable gate array”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
, “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
, “Circuit partitioning with logic perturbation”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
, “Cost-free scan: a low-overhead scan path design methodology”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.
, “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
, “Routing on regular segmented 2-D FPGAs”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
, “Clock skew optimization for ground bounce control”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
, “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
, “Graph based analysis of 2-D FPGA routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
, “Multilevel logic synthesis for arithmetic functions”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “Perturb and simplify: multilevel Boolean network optimizer”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
, “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
, “Time-multiplexed routing resources for FPGA design”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
, “Boolean functions classification via fixed polarity Reed-Muller forms”, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
, “Circuit optimization by rewiring”, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
, “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
