Publications
“Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.
, “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
, “Congestion minimization during placement without estimation”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
, “Sizing power/ground meshes for clocking and computing circuit components”, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
, “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
, “Interconnect resource-aware placement for hierarchical FPGAs”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
, “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
, “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
, “Single-pass redundancy-addition-and-removal”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
, “Wave steered FSMs”, in Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000, pp. 270 -276.
, “Circuit optimization by rewiring”, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
, “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
, “Wave pipelining YADDs-a feasibility study”, in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999, pp. 559 -562.
, “Wave steering in YADDs: a novel non-iterative synthesis and layout technique”, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
, “Boolean functions classification via fixed polarity Reed-Muller forms”, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
, “Clock skew optimization for ground bounce control”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
, “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
, “Graph based analysis of 2-D FPGA routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
, “Multilevel logic synthesis for arithmetic functions”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “Perturb and simplify: multilevel Boolean network optimizer”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
, “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
, “Time-multiplexed routing resources for FPGA design”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
, “Circuit partitioning with logic perturbation”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
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