Publications

Found 5 results
Filters: Keyword is fault simulation  [Clear All Filters]
1999
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
2004
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay fault diagnosis using timing information”, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
2005
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
2006
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Analysis and methodology for multiple-fault diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.
2008
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.