Publications

Found 4 results
Filters: Keyword is logic arrays  [Clear All Filters]
Conference Paper
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “On computational complexity of a detailed routing problem in two dimensional FPGAs”, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
Y. - L. Wu and Marek-Sadowska, M., “An efficient router for 2-D field programmable gate array”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
Y. Ran and Marek-Sadowska, M., “The magic of a via-configurable regular fabric”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 338 - 343.
Journal Article
Y. Ran and Marek-Sadowska, M., “Designing via-configurable logic blocks for regular fabric”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 1 -14, 2006.