Publications

Found 21 results
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S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., Perturb and simplify: multilevel Boolean network optimizer, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
S. - C. Chang, Cheng, D. I., and Marek-Sadowska, M., Minimizing ROBDD size of incompletely specified multiple output functions, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
S. - C. Chang and Marek-Sadowska, M., Technology mapping via transformations of function graphs, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.
D. I. Cheng and Marek-Sadowska, M., Verifying equivalence of functions with unknown input correspondence, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 81 -85.
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A hybrid methodology for switching activities estimation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
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S. Grygiel, Perkowski, M., Marek-Sadowska, M., Luba, T., and Jozwiak, L., Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
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C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., Logic synthesis for engineering change, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
C. - C. Lin and Marek-Sadowska, M., On designing universal logic blocks and their application to FPGA design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
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L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., Pipelining sequential circuits with wave steering, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
N. Modi and Marek-Sadowska, M., ECO-Map: Technology remapping for post-mask ECO using simulated annealing, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
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Y. Ran, Kondratyev, A., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, vol. 2, pp. 1192 - 1197 Vol.2.
Y. Ran, Kondratyev, A., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
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C. - C. Tsai and Marek-Sadowska, M., Boolean functions classification via fixed polarity Reed-Muller forms, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
C. - C. Tsai and Marek-Sadowska, M., Multilevel logic synthesis for arithmetic functions, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
C. - C. Tsai and Marek-Sadowska, M., Generalized Reed-Muller forms as a tool to detect symmetries, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
C. - C. Tsai and Marek-Sadowska, M., Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
C. - C. Tsai and Marek-Sadowska, M., Efficient minimization algorithms for fixed polarity AND/XOR canonical networks, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
C. - C. Tsai and Marek-Sadowska, M., Minimisation of fixed-polarity AND/XOR canonical networks, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.
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Y. - L. Wu and Marek-Sadowska, M., Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
Y. - L. Wu, Fan, H., Marek-Sadowska, M., and Wong, C. K., OBDD minimization based on two-level representation of Boolean functions, Computers, IEEE Transactions on, vol. 49, pp. 1371 -1379, 2000.