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Y. Ran and Marek-Sadowska, M., Designing via-configurable logic blocks for regular fabric, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 1 -14, 2006.
Y. Ran and Marek-Sadowska, M., An integrated design flow for a via-configurable gate array, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.