Publications

Found 5 results
Filters: Keyword is circuit optimisation and Author is Chih-Wei Chang  [Clear All Filters]
Journal Article
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
Conference Paper
C. - W. Chang, Wang, K., and Marek-Sadowska, M., “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
C. - W. Chang, Hu, B., and Marek-Sadowska, M., “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
C. - W. Chang and Marek-Sadowska, M., “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.