Publications
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Filters: Keyword is circuit CAD and Author is Sao-Jie Chen [Clear All Filters]
“Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
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