Publications

Found 3 results
Filters: Keyword is logic simulation  [Clear All Filters]
1999
A. Mukherjee, Sudhakar, R., Marek-Sadowska, M., and Long, S. I., “Wave steering in YADDs: a novel non-iterative synthesis and layout technique”, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
2004
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay fault diagnosis using timing information”, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
2005
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.