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C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., A new reasoning scheme for efficient redundancy addition and removal, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Postlayout logic restructuring using alternative wires, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Circuit optimization by rewiring, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
C. - W. Chang and Marek-Sadowska, M., Single-pass redundancy-addition-and-removal, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
C. - W. Chang and Marek-Sadowska, M., ATPG-based logic synthesis: an overview, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
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C. - C. Tsai and Marek-Sadowska, M., Logic synthesis for testability, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.