Publications

Found 2 results
Filters: Keyword is gate delay  [Clear All Filters]
2003
D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Temporofunctional crosstalk noise analysis, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
1990
S. Lin and Marek-Sadowska, M., An accurate and efficient delay model for CMOS gates in switch-level timing analysis, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.