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A. Mukherjee and Marek-Sadowska, M., Clock and power gating with timing closure, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., Delay and area optimization in standard-cell design, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.