Publications

Found 9 results
Filters: Keyword is minimisation of switching nets  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
C
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
S. - C. Chang, Cheng, D. I., and Marek-Sadowska, M., “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
H
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Crosstalk minimization for multiple clock tree routing”, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
L
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
C. - C. Lin, Chen, K. - C., Cheng, D. I., and Marek-Sadowska, M., “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
S
A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
T
C. - C. Tsai and Marek-Sadowska, M., “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
W
Y. - L. Wu and Marek-Sadowska, M., “Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
Y. - L. Wu, Fan, H., Marek-Sadowska, M., and Wong, C. K., “OBDD minimization based on two-level representation of Boolean functions”, Computers, IEEE Transactions on, vol. 49, pp. 1371 -1379, 2000.