Publications
Found 30 results
Filters: Keyword is integrated circuit design [Clear All Filters]
, “Analysis of process variation's effect on SRAM's read stability”, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -610.
, “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
, “Benefits and costs of power-gating technique”, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
, “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
, “Crosstalk noise in FPGAs”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
, “Designing a via-configurable regular fabric”, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 2004, pp. 423 - 426.
, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
, “ECO-Map: Technology remapping for post-mask ECO using simulated annealing”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
, “Efficient closed-form crosstalk delay metrics”, in Quality Electronic Design, 2002. Proceedings. International Symposium on, 2002, pp. 431 - 436.
, “Efficient delay calculation in presence of crosstalk”, in Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on, 2000, pp. 491 -497.
, “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
, “Gain-based technology mapping for discrete-size cell libraries”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
, “Individual wire-length prediction with application to timing-driven placement”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
, “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
, “An integrated design flow for a via-configurable gate array”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
, “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
, “Low power, high throughput network-on-chip fabric for 3D multicore processors”, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, pp. 453 -454.
, “The magic of a via-configurable regular fabric”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 338 - 343.
, “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
, “Multilevel logic synthesis for arithmetic functions”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
, “On-chip power supply network optimization using multigrid-based technique”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
, “On-chip power-supply network optimization using multigrid-based technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 407 - 417, 2005.
, “Power supply noise aware workload assignment for multi-core systems”, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
, “Power/ground mesh area optimization using multigrid-based technique [IC design]”, in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
, “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
