Publications

Found 8 results
Filters: Keyword is logic circuits and Author is Malgorzata Marek-Sadowska  [Clear All Filters]
1993
C. - C. Tsai and Marek-Sadowska, M., Efficient minimization algorithms for fixed polarity AND/XOR canonical networks, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
1994
C. - C. Tsai and Marek-Sadowska, M., Minimisation of fixed-polarity AND/XOR canonical networks, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.
1995
D. I. Cheng, Lin, C. - C., and Marek-Sadowska, M., Circuit partitioning with logic perturbation, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
1996
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A new hybrid methodology for power estimation, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
1998
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A hybrid methodology for switching activities estimation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
2004
K. Wang and Marek-Sadowska, M., Potential slack budgeting with clock skew optimization, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
2006
Q. Liu and Marek-Sadowska, M., Semi-individual wire-length prediction with application to logic synthesis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 611 - 624, 2006.
2011
M. Marek-Sadowska and Qiu, X., A study on cell-level routing for VeSFET circuits, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.