Publications
, “Efficient closed-form crosstalk delay metrics”, in Quality Electronic Design, 2002. Proceedings. International Symposium on, 2002, pp. 431 - 436.
, “SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
, “An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
