Publications

Found 9 results
Filters: First Letter Of Title is G  [Clear All Filters]
Conference Paper
B. Hu, Watanabe, Y., and Marek-Sadowska, M., “Gain-based technology mapping for discrete-size cell libraries”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
T. Xiao and Marek-Sadowska, M., “Gate sizing to eliminate crosstalk induced timing violation”, in Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, 2001, pp. 186 -191.
N. Funabiki, Singh, A., Mukherjee, A., and Marek-Sadowska, M., “A global routing technique for wave-steered design methodology”, in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, pp. 430 -436.
Y. - L. Wu and Marek-Sadowska, M., “Graph based analysis of FPGA routing”, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
Journal Article
M. Marek-Sadowska and Kuh, E. S., “General channel-routing algorithm”, Electronic Circuits and Systems, IEE Proceedings G, vol. 130, pp. 83 -88, 1983.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
C. - C. Tsai and Marek-Sadowska, M., “Generalized Reed-Muller forms as a tool to detect symmetries”, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
J. - T. Li and Marek-Sadowska, M., “Global Routing for Gate Array”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “Graph based analysis of 2-D FPGA routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.