Publications

Found 231 results
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M. Marek-Sadowska and Lin, S., Timing driven placement, in Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on, 1989, pp. 94 -97.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology, in Test Conference, 2006. ITC '06. IEEE International, 2006, pp. 1-10.
S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., Timing analysis considering IR drop waveforms in power gating designs, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., Time-multiplexed routing resources for FPGA design, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., Is there always performance overhead for regular fabric?, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
C. - W. Chang and Marek-Sadowska, M., Theory of wire addition and removal in combinational Boolean networks, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Test-point insertion: scan paths through functional logic, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
D. Chang, Lee, T. - C., Marek-Sadowska, M., Aikyo, T., and Cheng, K. - T., A Test Synthesis Approach To Reducing Ballast Dft Overhead, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Test point insertion: scan paths through combinational logic, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Temporofunctional crosstalk noise analysis, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
S. - C. Chang and Marek-Sadowska, M., Technology mapping via transformations of function graphs, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.
S. - C. Chang and Marek-Sadowska, M., Technology mapping and circuit depth optimization for field programmable gate arrays, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4.
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B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., Synthesis and placement flow for gain-based programmable regular fabrics, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
M. Marek-Sadowska, Switch box routing: a retrospective, Integr. VLSI J., vol. 13, pp. 39–65, 1992.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
M. Marek-Sadowska and Qiu, X., A study on cell-level routing for VeSFET circuits, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.
A. Todri and Marek-Sadowska, M., A study of reliability issues in clock distribution networks, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
Q. Liu and Marek-Sadowska, M., A study of netlist structure and placement efficiency, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 762 - 772, 2005.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., A study of decoupling capacitor effectiveness in power and ground grid networks, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., Stepwise equivalent conductance circuit simulation technique, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.
V. S. Nandakumar, Newmark, D., Zhan, Y., and Marek-Sadowska, M., Statistical static timing analysis flow for transistor level macros in a microprocessor, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., Starbist Scan Autocorrelated Random Pattern Generation, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., STAR-ATPG: a high speed test pattern generator for large scan designs, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Star test: the theory and its applications, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
D. I. Cheng, Marek-Sadowska, M., and Cheng, K. - T., Speeding up power estimation by topological analysis, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.

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