Publications

Found 228 results
Filters: Author is Malgorzata Marek-Sadowska  [Clear All Filters]
2008
N. Modi and Marek-Sadowska, M., ECO-Map: Technology remapping for post-mask ECO using simulated annealing, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., Fast and simple modeling of non-rectangular transistors, in Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, 2008, vol. 7122.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Improving the Resolution of Single-Delay-Fault Diagnosis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
H. Jiang and Marek-Sadowska, M., Power gating scheduling for power/ground noise reduction, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., Power supply noise aware workload assignment for multi-core systems, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
A. Todri and Marek-Sadowska, M., A study of reliability issues in clock distribution networks, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., Is there always performance overhead for regular fabric?, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., Timing analysis considering IR drop waveforms in power gating designs, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Timing-Aware Multiple-Delay-Fault Diagnosis, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
2007
A. Todri, Marek-Sadowska, M., and Chang, S. - C., Analysis and optimization of power-gated ICs with multiple power gating configurations, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., An Efficient Mechanism for Performance Optimization of Variable-Latency Designs, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
A. Todri, Chang, S. - C., and Marek-Sadowska, M., Electromigration and voltage drop aware power grid optimization for power gated ICs, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, 2007, pp. 391 -394.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., Engineering change using spare cells with constant insertion, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
W. Maly, Yi-Wei Lin, and Marek-Sadowska, M., OPC-Free and Minimally Irregular IC Design Style, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 954 -957.
H. Jiang and Marek-Sadowska, M., Power-Gating Aware Floorplanning, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
C. - W. Chang and Marek-Sadowska, M., Theory of wire addition and removal in combinational Boolean networks, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
2006
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Analysis and methodology for multiple-fault diagnosis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.
C. - K. Tsai and Marek-Sadowska, M., Analysis of process variation's effect on SRAM's read stability, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -610.
V. Mehta, Wang, Z., Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay fault diagnosis for nonrobust test, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -472.
Y. Ran and Marek-Sadowska, M., Designing via-configurable logic blocks for regular fabric, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 1 -14, 2006.
H. Jiang and Marek-Sadowska, M., Power/Ground Supply Network Optimization for Power-Gating, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
Q. Liu and Marek-Sadowska, M., Semi-individual wire-length prediction with application to logic synthesis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 611 - 624, 2006.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology, in Test Conference, 2006. ITC '06. IEEE International, 2006, pp. 1-10.
Y. Ran and Marek-Sadowska, M., Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 998 -1009, 2006.
2005
H. Jiang, Marek-Sadowska, M., and Nassif, S. R., Benefits and costs of power-gating technique, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.

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