Publications

Found 228 results
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Journal Article
Y. - L. Wu, Fan, H., Marek-Sadowska, M., and Wong, C. K., OBDD minimization based on two-level representation of Boolean functions, Computers, IEEE Transactions on, vol. 49, pp. 1371 -1379, 2000.
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., A new reasoning scheme for efficient redundancy addition and removal, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
B. Hu and Marek-Sadowska, M., Multilevel fixed-point-addition-based VLSI placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.
C. - C. Tsai and Marek-Sadowska, M., Minimisation of fixed-polarity AND/XOR canonical networks, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.
A. Vittal and Marek-Sadowska, M., Low-power buffered clock tree design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., Logic synthesis for engineering change, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Layout Generator for Transistor-Level High-Density Regular Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
Q. Liu, Hu, B., and Marek-Sadowska, M., Individual wire-length prediction with application to timing-driven placement, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Improving the Resolution of Single-Delay-Fault Diagnosis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A hybrid methodology for switching activities estimation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., Graph based analysis of 2-D FPGA routing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
J. - T. Li and Marek-Sadowska, M., Global Routing for Gate Array, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
C. - C. Tsai and Marek-Sadowska, M., Generalized Reed-Muller forms as a tool to detect symmetries, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., General skew constrained clock network sizing based on sequential linear programming, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
M. Marek-Sadowska and Kuh, E. S., General channel-routing algorithm, Electronic Circuits and Systems, IEE Proceedings G, vol. 130, pp. 83 -88, 1983.
B. Hu and Marek-Sadowska, M., Fine granularity clustering-based placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
Y. Ran, Kondratyev, A., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
T. T. - K. Tarng, Marek-Sadowska, M., and Kuh, E. S., An Efficient Single-Row Routing Algorithm, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., Efficient circuit clustering for area and power reduction in FPGAs, ACM Trans. Des. Autom. Electron. Syst., vol. 7, pp. 643–663, 2002.
Y. Ran and Marek-Sadowska, M., Designing via-configurable logic blocks for regular fabric, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 1 -14, 2006.
C. - C. Lin and Marek-Sadowska, M., On designing universal logic blocks and their application to FPGA design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay-fault diagnosis using timing information, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
A. Vittal and Marek-Sadowska, M., Crosstalk reduction for VLSI, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 290 -298, 1997.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., Crosstalk in VLSI interconnections, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.

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