Publications

Found 37 results
Filters: Keyword is logic CAD  [Clear All Filters]
1999
A. Mukherjee, Marek-Sadowska, M., and Long, S. I., “Wave pipelining YADDs-a feasibility study”, in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999, pp. 559 -562.
A. Mukherjee, Sudhakar, R., Marek-Sadowska, M., and Long, S. I., “Wave steering in YADDs: a novel non-iterative synthesis and layout technique”, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
2000
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., “Wave steered FSMs”, in Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000, pp. 270 -276.
2001
C. - W. Chang, Hu, B., and Marek-Sadowska, M., “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., “Interconnect resource-aware placement for hierarchical FPGAs”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
C. - W. Chang, Wang, K., and Marek-Sadowska, M., “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
C. - W. Chang and Marek-Sadowska, M., “Single-pass redundancy-addition-and-removal”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
2002
C. - W. Chang and Marek-Sadowska, M., “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
B. Hu and Marek-Sadowska, M., “Congestion minimization during placement without estimation”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
A. Mukherjee, Wang, K., Chen, L. H., and Marek-Sadowska, M., “Sizing power/ground meshes for clocking and computing circuit components”, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
2003
A. Mukherjee and Marek-Sadowska, M., “Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.

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