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Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “On computational complexity of a detailed routing problem in two dimensional FPGAs”, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
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T. Xiao and Marek-Sadowska, M., “Crosstalk reduction by transistor sizing”, in Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific, 1999, pp. 137 -140 vol.1.

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