Publications
Found 42 results
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“In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
, “An efficient algorithm for local don't care sets calculation”, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667.
, “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
, “Fast post-placement rewiring using easily detectable functional symmetries”, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
, “Technology mapping and circuit depth optimization for field programmable gate arrays”, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4.
, “Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs”, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
, “Functional scan chain testing”, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
, “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
, “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
, “Partitioning sequential circuits on dynamically reconfigurable FPGAs”, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
, “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
, “Theory of wire addition and removal in combinational Boolean networks”, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
, “A Test Synthesis Approach To Reducing Ballast Dft Overhead”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
, “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
, “Who are the alternative wires in your neighborhood? (alternative wires identification without search)”, in GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI, 2001, pp. 103–108.
, “Circuit optimization by rewiring”, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
, “Temporofunctional crosstalk noise analysis”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
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