Publications
, “Incremental delay change due to crosstalk noise”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 120–125.
, “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
, “Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues”, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6A.4.1 -6A.4.9.
, “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
, “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
, “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
, “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
, “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
, “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
, “Minimizing inter-clock coupling jitter”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.
, “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
, “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
, “Modeling crosstalk in resistive VLSI interconnections”, in VLSI Design, 1999. Proceedings. Twelfth International Conference On, 1999, pp. 470 -475.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
, “Perturb And Simplify: Multi-level Boolean Network Optimizer”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
, “Perturb and simplify: optimizing circuits with external don't cares”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
, “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
, “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
, “Sequential permissible functions and their application to circuit optimization”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
, “Single-pass redundancy-addition-and-removal”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
, “Sizing power/ground meshes for clocking and computing circuit components”, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
, “Speeding up power estimation by topological analysis”, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
, “Speeding up power estimation by topological analysis”, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
