Publications

Found 228 results
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1996
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., Graph based analysis of 2-D FPGA routing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
C. - C. Tsai and Marek-Sadowska, M., Logic synthesis for testability, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.
C. - C. Tsai and Marek-Sadowska, M., Multilevel logic synthesis for arithmetic functions, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A new hybrid methodology for power estimation, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., Perturb and simplify: multilevel Boolean network optimizer, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
S. - C. Chang and Marek-Sadowska, M., Perturb and simplify: optimizing circuits with external don't cares, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Scan paths through functional logic, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
C. - C. Lin, Chen, K. - C., Marek-Sadowska, M., and Lee, T. - C., Sequential permissible functions and their application to circuit optimization, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Test point insertion: scan paths through combinational logic, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., Time-multiplexed routing resources for FPGA design, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
1997
C. - C. Tsai and Marek-Sadowska, M., Boolean functions classification via fixed polarity Reed-Muller forms, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
D. Chang and Marek-Sadowska, M., Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
A. Vittal and Marek-Sadowska, M., Crosstalk reduction for VLSI, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 290 -298, 1997.
S. Grygiel, Perkowski, M., Marek-Sadowska, M., Luba, T., and Jozwiak, L., Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
M. Perkowski, Marek-Sadowska, M., Jozwiak, L., Luba, T., Grygiel, S., Nowicka, M., Malvi, R., Wang, Z., and Zhang, J. S., Decomposition of multiple-valued relations, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 13 -18.
C. - C. Lin and Marek-Sadowska, M., On designing universal logic blocks and their application to FPGA design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
A. Vittal and Marek-Sadowska, M., Low-power buffered clock tree design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.
Y. - L. Wu, Chang, D., Marek-Sadowska, M., and Tsukiyama, S., Not necessarily more switches more routability [sic.], in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., Post-layout Logic Restructuring For Performance Optimization, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Postlayout logic restructuring using alternative wires, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
Y. - L. Wu and Marek-Sadowska, M., Routing for array-type FPGA's, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 506 -518, 1997.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Scan encoded test pattern generation for BIST, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., Starbist Scan Autocorrelated Random Pattern Generation, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
D. Chang, Lee, T. - C., Marek-Sadowska, M., Aikyo, T., and Cheng, K. - T., A Test Synthesis Approach To Reducing Ballast Dft Overhead, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
1998
C. - C. Lin, Marek-Sadowska, M., Lee, T. - C., and Chen, K. - C., Cost-free scan: a low-overhead scan path design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.

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