Publications
, “Multilevel expansion-based VLSI placement with blockages”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 558-564.
, “Fine granularity clustering for large scale placement problems”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.
, “Wire length prediction based clustering and its application in placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
, “mFAR: fixed-points-addition-based VLSI placement algorithm”, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 239–241.
, “Gain-based technology mapping for discrete-size cell libraries”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
, “Synthesis and placement flow for gain-based programmable regular fabrics”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
, “Multilevel fixed-point-addition-based VLSI placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.
, “FAR: fixed-points addition & relaxation based placement”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
, “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
, “Clock skew bounds estimation under power supply and process variations”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
, “Benefits and costs of power-gating technique”, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
, “Power gating scheduling for power/ground noise reduction”, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
, “Power/Ground Supply Network Optimization for Power-Gating”, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
, “Power-Gating Aware Floorplanning”, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
, “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
, “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
, “Engineering change using spare cells with constant insertion”, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
, “On-chip em-sensitive interconnect structures”, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
, “Variation-aware electromigration analysis of power/ground networks”, in Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, pp. 571 -576.
, “Global Routing for Gate Array”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
, “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
, “An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
, “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
, “Universal Logic Gate For Fpga Design”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.
