Publications
, “Technology mapping and circuit depth optimization for field programmable gate arrays”, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4.
, “Technology mapping via transformations of function graphs”, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.
, “Temporofunctional crosstalk noise analysis”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
, “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
, “A Test Synthesis Approach To Reducing Ballast Dft Overhead”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
, “A Test Synthesis Approach To Reducing Ballast Dft Overhead”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
, “Time-multiplexed routing resources for FPGA design”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
, “Timing analysis considering IR drop waveforms in power gating designs”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
, “Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
, “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 145 -150.
, “Verifying equivalence of functions with unknown input correspondence”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 81 -85.
, “Who are the alternative wires in your neighborhood? (alternative wires identification without search)”, in GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI, 2001, pp. 103–108.
, “Aggressor alignment for worst-case crosstalk noise”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, pp. 612 -621, 2001.
, “Buffer delay change in the presence of power and ground noise”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
, “Circuit optimization by rewiring”, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
, “Closed-Form Crosstalk Noise Delay Metrics”, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
, “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
, “Crosstalk in VLSI interconnections”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.
, “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
, “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
, “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
, “A hybrid methodology for switching activities estimation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
, “A hybrid methodology for switching activities estimation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
, “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
, “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
