Publications
, “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
, “Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs”, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
, “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
, “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
, “Postlayout logic restructuring using alternative wires”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
, “Postlayout logic restructuring using alternative wires”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
, “A Test Synthesis Approach To Reducing Ballast Dft Overhead”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
, “A Test Synthesis Approach To Reducing Ballast Dft Overhead”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
, “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “Perturb and simplify: multilevel Boolean network optimizer”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
, “Perturb and simplify: multilevel Boolean network optimizer”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
, “Perturb and simplify: optimizing circuits with external don't cares”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
, “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
, “Sequential permissible functions and their application to circuit optimization”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
, “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
, “Time-multiplexed routing resources for FPGA design”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
, “Circuit partitioning with logic perturbation”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
, “Cost-free scan: a low-overhead scan path design methodology”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.
, “An efficient algorithm for local don't care sets calculation”, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667.
, “An efficient algorithm for local don't care sets calculation”, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667.
, “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
, “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
, “Speeding up power estimation by topological analysis”, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
